The present invention relates to phase-locked loops, and more particularly to the sequential start-up of clock outputs provided by a phase-locked loop.
Phase locked-loops are an essential building block of many integrated circuits, providing periodic signals for data recovery, data transfer, and other clocking functions. They often supply a clock signal to one or more counters or dividers that divide a signal from a voltage controlled oscillator (VCO) to a lower frequency clock signal for distribution around an integrated circuit or system. These dividers provide clock outputs that may have the same or different frequencies as compared to one another.
It is also often desirable that two or more of these clocks have a known and predictable phase relationship with each other. For example, when high speed data is clocked in parallel into a lower speed first-in-first-out (FIFO) memory, it is important that the timing of the data is correct, such that FIFO set-up and hold times are met.
A proper phase relationship may be achieved by using a VCO that has multiple outputs at known phases to each other, for example a ring oscillator. Unfortunately, these ring and similar types of oscillators typically power up in an indeterminate state. That is, there is uncertainty as far as which output of ring oscillator toggles first following power up. Also, a different output may toggle first each time the circuit is powered up.
This uncertainty means that different counters driven different taps of a ring oscillator begin counting at different times each time power is applied. This is also true following an asynchronous reset of the counters. The result is that the phase relationship of the counter outputs may not be what is needed for proper circuit operation.
Accordingly, what is needed are circuits, methods, and apparatus for providing predictability in the start-up of clock circuits having desired phase relationships following a power up or reset.